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Remember aback accumulation a camera with a cellphone seemed daring? Or abacus a cellphone to a PDA? Such abstruse tricks relied on Moore’s Law, which holds that the cardinal of transistors on an IC doubles every 18 months. In the accretion world, accepting added transistors on a dent agency added acceleration and possibly added functions.But in abounding cases, those Moore’s Law ICs accord with abandoned 10 percent of the system. The added 90 percent is still there, assuming up as an adjustment of beefy detached acquiescent components—such as resistors, capacitors, inductors, antennas, filters, and switches—interconnected over a printed-circuit lath or two. Real miniaturization requires commodity more, and we accept it in the system-on-package (SOP) access we’re advancing at the Microsystems Packaging Analysis Centermost at the Georgia Institute of Technology, in Atlanta. SOP leapfrogs able-bodied above Moore’s Law. It combines ICs with micrometer-scale thin-film versions of detached components, and it embeds aggregate in a new blazon of amalgamation so baby that eventually handhelds will become anythingfrom multi- to megafunction devices. SOP articles will be developed not aloof for wireless communications, computing, and entertainment. Outfitted with sensors, SOPs could be acclimated to ascertain all abode of substances, baneful and benign, including chemicals in the environment, in food, and in the animal body.

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This aftermost appliance will see the aggregation of biology, chemistry, and agenda technology to aftermath capsules baby abundant to be alien into the animal anatomy to adviser claimed bloom daily. A abridged could be used, for example, to analysis basic signs and adviser ambit such as glucose levels, claret pressure, and alike signs of cancer. The abridged would afresh wirelessly acquaint the person’s bloom cachet to a Web terminal alfresco the anatomy or, via the Internet, to a physician (or to anyone, anywhere). Fitted with a reservoir, the abridged could additionally bear drugs at programmed intervals to alleged places aural the body.

That tiny anatomy abridged is absolutely a acute product, and we can apprehend abounding others. Imagine, for example, a home ball and ascendancy hub—a accessory that combines voice, video, data, sensing, and ascendancy functions. It could accommodate a home computer, a cellphone, ecology and added sensors, a bloom ecology device, and a accessory TV receiver, to name aloof some possibilities. A wireless broadband affiliation would articulation the adjustment to the Internet, and the hub would serve as the alien ascendancy for all the home’s appliances.

Yet the hub would be as baby as a acclaim card.

We anticipate a megafunction SOP assemblage congenital with microscale apparatus that would be the admeasurement of an Intel Pentium processor, which comes in a collapsed backpack 35 centimeters on a side. Or, congenital with nanoscale technologies, an SOP could be as baby as a millimeter on a side. SOP articles will attain such baby sizes because the technology attacks the 90 percent of the system—the alleged 90 percent problem—that is not dent [see diagram, “Many in One”].

In a cellphone, for example, that 90 percent about adds up to some 400 detached acquiescent apparatus and their metal interconnections, all attached to a about ample printed-circuit board. And, of course, some systems will accept bags of detached apparatus sitting on ambit boards.

SOP technology represents a radically altered access to systems. It shrinks beefy ambit boards with their abounding apparatus and makes them about disappear. In effect, SOP sets up a new law for adjustment integration. It holds that as the apparatus compress and the boards all but disappear, the basic anatomy will bifold every year or so, and the cardinal of adjustment functions in an SOP amalgamation will access in the aforementioned proportion. Thus, SOP technology yields far added in adjustment miniaturization than can be accepted from Moore’s Law, which deals abandoned with transistors in ICs [see blueprint below, “Growing Faster”].

Growing Faster: Adjustment affiliation appliance system-on-package (SOP) technology from Georgia Tech’s Microsystems Packaging Analysis Centermost will see “More Than Moore’s Law” booty hold, as abstinent by basic density. From about 50 apparatus per aboveboard centimeter in 2004, basic anatomy will ascend to about a actor per aboveboard centimeter by 2020. Functional adjustment anatomy will amplify similarly.

Squeezing so abundant into tiny spaces is our mission at Georgia Tech. If we accept our way, articles will compress by abundant added than the agency of 10 about accepted every few years now. Instead, they will compress by factors of abounding hundreds and alike bags in the aforementioned time frame.

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We began this analysis in 1993 with a angle to the U.S. National Science Foundation for an Engineering Analysis Center, which the NSF afresh funded. Today we are not abandoned in this endeavor: advisers about the apple are appliance SOP to amalgamate assorted technologies in new, unusual, and cost-effective ways. Everyone is afterwards ultracompact articles congenital with any aggregate of digital, analog, radio-frequency, and alike optical circuitry, as able-bodied as a array of sensors.

For added than 40 years, ambit designers accept counted on the abiding access in transistor anatomy in their following of con­vergence. For example, engineers at Texas Instruments are architecture absolute signal-processing subsystems with assorted functions on a dent of silicon—a system-on-chip, or SOC, as it’s called. Designing such a dent has its abstruse problems, too, decidedly if agenda argumentation and anamnesis for ciphering charge be accumulated with analog and RF communications circuitry. Usually, these antithetical circuits not abandoned accomplish at altered voltages but additionally crave altered processing accomplish during manufacture. Complicating affairs further, analog and RF circuits charge be electrically abandoned from agenda ones. Architecture time and complexity, forth with artifact costs and time to market, can skyrocket.

At Georgia Tech we booty advantage of amalgamation integration. We annihilate the alone acquiescent basic packages—the adamantine atramentous tiles you see on the ample adjustment lath central your PC, DVD player, or cellphone. Those bales admeasurement anywhere from a division of a millimeter to as ample as 3 cm on a ancillary and a millimeter or two high. Instead of appliance them, we catechumen the acquiescent elements to bare, thin-film apparatus abandoned micrometers blubbery and bury them in our multilayered adjustment package. Such thin-film apparatus are anywhere from a thousandth to a millionth of their aboriginal packaged size. Further, in our latest research, we accept alone beefy IC packages, too, by embedding their bald chips in the SOP package. We alike barber the chips bottomward to a array of 25 micrometers, from their aboriginal 1 millimeter.

SOP does abroad with the beefy adjustment lath and makes the amalgamation the centerpiece of adjustment integration. Awful integrated, this multilayered amalgamation holds all the parts—thinned, bald IC chips; acquiescent thin-film components; and abject and interconnections.

The aftereffect is that we accession the basic count—and the cardinal of functions—per assemblage aggregate able-bodied above what is accessible by blank the amalgamation and artlessly relying on Moore’s Law for ICs. But abate admeasurement is not the abandoned benefit. Admeasurement abridgement additionally allows for abundant faster chip-to-chip signals at lower currents and voltages—which cuts ability dissipation.

Note, too, that with SOP we’re not bound to silicon or any accurate technology; we can use whatever we wish. Accession account is that we don’t force antithetical technologies to conjugate on a distinct allotment of silicon, as may appear in an SOC architecture that tries to put abounding functions on a distinct IC chip.

We use accessories bogus of silicon, gallium arsenide, or silicon germanium—whatever actual is best ill-fitted for our ICs and detached apparatus [again, see “ ”]. For example, we use silicon ICs for agenda circuits and some RF devices, such as amplifiers and oscillators. In the package, we bury antennas, capacitors, inductors, resistors, filters, crystals, and waveguides. We bury these genitalia as attenuate films in the layers of the package. For biosensing applications, we anatomy sensors of tiny resonators, nanotubes, nanobelts, and microelectromechanical systems (MEMS). And aback breakthrough and atomic accessories become available, we’ll be able to use them, too.

Because we’re not affected to use any accurate technology, the time it takes to architecture and accumulate a adjustment is abundant beneath than before, and time to bazaar is beneath as well. Further, the dent and amalgamation of an SOP-based adjustment are advised and bogus in parallel—not serially, one afterwards another—which saves time and money.

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We charge not accommodation speed, cost, time to market, or reliability. Such compromises charge be bogus aback antithetical technologies are accumulated in a distinct IC. Yet our SOP with its abounding functions will be no bigger than the beefy amalgamation of an SOC, which cannot amalgamate about as abounding technologies as we can. Our SOP can alike accommodate cost-effective chip-to-chip optoelectronics, replacing nut wire with optical fiber, and can accommodate miniature waveguides, gratings, lasers, and detectors.

To anatomy an SOP for, say, a mixed-signal, multifunction system, we can accumulate assorted adjustment functions on a distinct substrate. We alpha with an ultrathin yet annealed blended substrate. Aing we drop layers of dielectrics and conductors as able-bodied as the thin-film components, including capacitors, resistors, inductors, filters, switches, and waveguides. But clashing a silicon wafer, which is round, our SOP dent is square, measuring, so far, 300 mm on a side. Completed wafers are electrically activated and diced into aboveboard or ellipsoidal adjustment bales barometer anywhere from 1 to 2.5 cm on a side. Some ICs of silicon or gallium arsenide or added material—whether meant for processors or memory—can be affiliated to the top apparent of the SOP with accustomed lead-free adhesive or nut interconnects.

Our SOP abstraction goes able-bodied above alone agreement assorted chips in a package, as IBM did some 20 years ago in its bowl multichip module. Until our SOP came along, IBM’s MCM was the best awful dent amalgamation in existence, with nut abject for aing ICs. But it has no anchored thin-film apparatus as does an SOP, and it requires a adjustment board. Thus, while an SOP attacks the 90 percent allotment of the adjustment problem, an MCM does not.

SOP is additionally altered from a system-in-package (SIP), accession miniaturization abode actuality deployed by best IC, package, and cellphone companies. In the SIP approach, bald or packaged IC chips are ample on top of anniversary added in a three-dimensional arrangement. But SIPs abode abandoned 10 percent of the adjustment botheration and avoid the botheration of beefy acquiescent components. An MCM or an SIP charge still bung into a acceptable adjustment board.

Our SOP has abounding advantages over those added approaches. Perhaps the bigger allowances are that, in a cellphone, for example, we accept none of those 400 acquiescent apparatus to assemble, and there is no adjustment board, aback the lath becomes the package. And the amalgamation can authority silicon agenda ICs alongside ICs bogus of added materials. Such adequacy is aing to absurd for an SOC and has not been approved for an SIP.

Because an SOP uses abstracted chips for its altered functions, designs are simpler and accomplishment time beneath than for an SOC. And for accretion applications we can alike aish the space-eating and high-resistance affairs on the ICs that administer alarm and power. Instead, we put those affairs in our package. We can additionally move nanoscale abject that is on dent into the package. There, such affairs can be added and thicker than what can be analytic bogus on chip; wire attrition is lower, convalescent acceleration and abbreviation the activity absent to heat.

An SOP architecture relies on abounding attenuate accumbent layers of dielectrics captivation conductors and components. For accretion applications, we drop assorted layers of ultra-low-loss and ultra-low-dielectric-constant insulators forth with electroplated nut interconnects bogus of 2- to 5-mm-wide nut traces. The insulators are bogus of accepted polymers, such as epoxies, or added avant-garde polymers, such as polyimide or benzo­cyclobutene, that accept outstanding dielectric properties.

We additionally bury 1-µm-thick decoupling capacitors actual aing to anniversary IC dent to abbreviate ability noise. To accomplish this, we invented atypical bowl decoupling capacitors that can be candy at about low temperatures. Traditionally, ceramics accept the accomplished dielectric connected and everyman dielectric loss, compared, for example, with amoebic materials. Ceramics’ check is that the capacitors charge be bogus at actual aerial temperatures, able-bodied above what is archetypal of electronics fabrication. Capacitors bogus of amoebic materials, on the added hand, can be bogus at lower temperatures but ache from actual low dielectric constants. We developed capacitors with ceramiclike backdrop but bogus at the temperatures acclimated for amoebic abstracts in an avant-garde low-temperature actinic action referred to as a hydrothermal process.

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For RF applications, we anatomy organic-compatible thin-film capacitors that are abiding because of their low temperature accessory of capacitance. We additionally accumulate high-value resistors that are abiding because they accept a low temperature accessory of resistance. We anatomy high-quality-­factor inductors far above to any bogus on silicon. We use a array of both thin-film and blended technologies to accomplish these properties. Thin-film artifact processes accommodate sputtering, electroplating, and sol gel, as able-bodied as the hydrothermal process.

For optical applications, we drop attenuate films to anatomy waveguides, optical gratings, mirrors, and lenses. For analysis biological functions in the body, we accept developed silicon, zinc oxide, and carbon nanotube sensors that selectively ascertain the chemicals of anatomy fluids. [See chart, “Embedded Thin-Film Apparatus Developed for System-on-Package.”]

We accept additionally congenital abundant analysis cartage that amalgamate RF, digital, and optical functions. The Intelligent Arrangement Anchorperson was the aboriginal such mixed-signal SOP, advised and congenital at the Microsystems Packaging Analysis Centermost in 2003. We acclimated it to apprentice how to accompanying design, develop, and optimize our abstracts and processes. It was a 75- by 50-mm multilayer sandwich, 1.2 mm thick, bogus of thin-film abstracts and anchored alive and acquiescent apparatus and alive accessories in bales on the top surface.

We congenital it to address a accelerated agenda arresting on an RF carrier over an optical access to advice us accept the architecture and interface issues inherent in accumulation these technologies. The assemblage consists of a field-programmable-gate-array (FPGA) IC for the transmitter and accession for the receiver.

Each IC supports 16 channels, anniversary with a acceleration of 155 megabits per second. The transmitter achievement is multiplexed to accomplish a 2.4-gigabit-per-second agenda abstracts amount that modulates a 5.8â’’gigahertz RF carrier. The articulate arresting is transferred to the optical circuitry, which consists of a bald laser diode, waveguide, and photodetector.

The laser diode converts the signals, which are afresh transmitted as ablaze through the waveguide to the photodetector. Adapted at the photodetector, electrical signals acknowledgment to the analog section, breadth they are adapted aback into a agenda abstracts beck and accustomed by the FPGA. In the agenda breadth the abstracts are compared with the aboriginal transmitted data. The streams should be identical.

The abstinent waveforms on the bore surpassed the architecture goals, advertence the robustness of our process. For example, the agenda block was advised for a 2.4-Gb/s agenda abstracts rate, but we begin we could accelerate a abstracts beck at up to 3.1 Gb/s. Similarly, the optical waveguide accurate a 10-Gb/s abstracts amount with basal degradation.

The eight thin-film layers of the anchorperson adjustment lath accommodate four dielectric layers captivation nut interconnects. Abject patterns are produced on altered ­layers with avant-garde photolithographic printed-wiring techniques. Microvias affix the alive affairs to agenda and RF dent both aural the amalgamation and to ICs on the surface. Thin-film capacitors deposited on one of the board’s abject layers act as decoupling capacitors to aish ability noise. With our techniques, we commonly accomplished densities of 400 components per aboveboard centimeter, a amount afresh bigger to 600–1000/cm2. We apprehend to ability 10 000/cm2 aural a decade. Until recently, the basic anatomy of cyberbanking systems on accepted ambit boards stood at about 50–100/cm2.

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Since we began developing the SOP abstraction in 1993, we accept formed with added than 100 electronics companies from the United States, Japan, Korea, and Europe. Included are Avant-garde Micro Devices, Asahi, Ericsson, Ford, Hitachi, IBM, Intel, Matsushita, Motorola, NEC, Nokia, Samsung, Sony, and Texas Instruments. In addition, added than 70 advisers accept appear as visiting engineers to our centermost to abstraction SOP and its appliance to their assorted requirements.

So far, at atomic 50 companies accept taken genitalia of our technology and activated them to their automotive, computer, consumer, military, and wireless applications. We accept additionally congenital a cardinal of analysis cartage for altered companies focused on amalgam altered combinations of analog, digital, RF, optical, and sensor apparatus in a distinct package.

Motorola, for example, which was one of the Packaging Analysis Center’s founding partners, uses genitalia of SOP technology in two models of its GSM/General Packet Radio Service quad-band cellphones to accretion about a 40 percent abridgement in lath area. The bore contains all the analytical cellphone functions: RF processing, base-band arresting processing, ability management, and audio and anamnesis sections. Not abandoned does the bore chargeless up amplitude for new features, it is additionally the abject about which new cellphones with altered shapes and appearance (camera or Bluetooth, for instance) can be rapidly designed. Motorola calls its amalgamation a system-on-module (SOM), for which it developed its own custom embedded-capacitor technology. It letters it has alien added than 20 actor SOM-based phones.

SOP analysis is blooming about the world. At the Institute of Microelectronics in Singapore, for example, Mahadevan Iyer and his co-workers accept congenital an optoelectronic SOP advised for accelerated communications amid a arrangement and a home or office. The access is hardly altered from ours, with optical circuits bogus of silicon. The adjustment transmitted abstracts at 1 GHz. Someday such a accessory ability accomplish at hundreds of gigabits per second.

At the Interuniversity Microelectronics Center, in Leuven, Belgium, Robert Mertens and colleagues are belief the best blazon of RF antenna to anatomy in an SOP for a ambit of wireless communications articles yet to be introduced.

At the University of Arkansas, in Fayetteville, Len Schaper and Richard K. Ulrich developed techniques for burying capacitors, resistors, and inductors in the layers of their SOP board. They bent that about all the attrition and abundant of the capacitance bare for a adjustment can be anchored in the lath appliance vacuum-­deposition processes archetypal of the IC industry.

At the Royal Institute of Technology, in Stockholm, Sweden, Hannu Tenhunen and his accumulation are comparing the amount of an SOP to the amount of an SOC-based adjustment to bigger accept SOP’s amount advantages. And at Georgia Tech we accept activated avant-garde and bargain actinic processes to anatomy added than 20 thin-film digital, RF, optical, and sensor apparatus for SOPs. Included are anchored capacitors in the microfarad range, up from the nanofarad, breadth they had been.

The aing footfall for SOP is to add optical signaling amid chips central the amalgamation by sending ablaze signals through congenital optical waveguides. This way, a dent will be able to barter abstracts with a anamnesis dent at processor alarm rates, rather than at the few hundred megahertz accessible now.

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The capital botheration with optoelectronics has not been achievement but aerial cost. However, we can abate amount by architecture SOPs in batches. For example, as is done for ICs, hundreds of baby optoelectronic SOPs could be bogus on a distinct ample lath of 400 by 500 mm. Alone bales measuring, say, 25 mm on a ancillary could afresh be cut from the lath abundant as alone dies are cut from a ample silicon wafer.

In accession to waveguides, we accept congenital complete thin-film, chip-to-chip optoelectronic systems that accommodate lasers, optical gratings for selecting specific wavelengths, microlenses for absorption ablaze assimilate gratings, and photodetectors. Best of the structures accept been bogus with light-sensitive polymers and lithographic techniques agnate to those acclimated to accomplish ICs.

Three developments are needed, however, if the SOP abstraction is to accomplish on a ample scale. First, architecture accoutrement charge be developed for the accompanying architecture of digital, analog, and optical circuits forth with the package. Although accoutrement abide for designing alone agenda and analog circuits and for boards themselves, none abide for designing a accomplished adjustment like ours. Georgia Tech is ambience up an industry bunch to focus on developing such tools. And to advance SOP to the aing generation, we are additionally alignment several industry consortia on anchored alive and acquiescent components, alloyed arresting testing, nanometer abstracts and packaging, and thermal actual interfaces, amid others.

The additional development that’s bare would be a change in today’s IC- and system-package manufacturing. Today, semiconductor companies architecture and accumulate ICs but usually await on alfresco companies for their packages. Adjustment companies architecture their systems while counting on packaged ICs from semiconductor companies, adjustment boards from lath companies, and the accumulation of the absolute adjustment by arrangement manufacturers. But because of the way an SOP is advised and integrated, it charge be developed for artifact at the aforementioned time. The accomplishment archetypal will accordingly accept to change if the SOP adjustment is anytime to become mainstream.

The third change bare deals with action technologies. SOP substrates are a hybrid: they charge a apple-pie allowance like those for ICs, thin-film processes forth with low-cost, large-area lath processes. Accordingly, a cardinal of altered accomplishment techniques for SOPs are emerging, including an SOP-like amalgamation with thin-film degradation on silicon wafers by Philips; amoebic boards by Shinko, Ibiden, and Matsushita; and bowl boards by Murata and TDK.

At Georgia Tech we accept that the bazaar for multifunctional articles and the advantages of designing chips and adjustment bales accordingly are so acute that companies will aloof accept to architecture and accumulate aggregate together. And as the SOP abstraction takes off, design-tool and artifact houses will about-face their absorption to developing able programs for circumstantial architecture and avant-garde manufacturing, aloof as they did in the accomplished decade aback the SOC was in its infancy.

Acknowledgment: The columnist wishes to acknowledge his Georgia Tech aggregation of faculty, engineers, students, and assembly from industry for their contributions included in this article, and both the Georgia Analysis Alliance and the National Science Foundation—Engineering Analysis Centers for their allotment of SOP technology for added than a decade.

RAO R. TUMMALA, an IEEE Fellow, is a affiliate of the National Academy of Engineering and is the Pettit Chair Professor in Microsystems Packaging at the Georgia Institute of Technology, in Atlanta. He is additionally the founding administrator of the Microsystems Packaging Analysis Center, one of the U.S. National Science Foundation’s 22 Engineering Analysis Centers. Afore aing the Georgia Tech faculty, he was an IBM Fellow and administrator of the company’s Avant-garde Packaging Technology Laboratory.

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The May 2004 IEEE Transactions on Avant-garde Packaging was adherent to system-on-package research. See R. Tummala et al., “SOP for Miniaturized Mixed-Signal Computing, Communication, and Customer Systems of the Aing Decade,” pp. 250–267, and R. Tummala, “SOP: What It Is and Why?” pp. 241–249.

Another commodity anecdotic a accelerated wireless device, by R. Tummala and J. Laskar, “Gigabit wireless: system-on-package technology,” is in Proceedings of the IEEE, Vol. 92, 2004, pp. 376–387.

“Packages Go Vertical,” IEEE Spectrum, August 2001, describes system-in-package technology. “Chips Go Vertical,” Spectrum, March 2004, looks at methods for stacking chips.

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