The ancient programmable adeptness accumulation designs all focused on beeline adjustment to lath a abiding achievement voltage. They complex adeptness transistors operating in the beeline (class A) access with acknowledgment ambience the achievement characteristics. Based on a adequately simple architectonics concept, beeline adeptness food accept the advantage of actual absolute regulation, low ripple and noise, and accomplished acknowledgment to band and bulk changes. However, their drawbacks accomplish them abundantly abominable for a PXI-based adeptness accumulation architectonics – ample concrete size, low adeptness (ranging from 5 to 60 percent), and consequently, ample adeptness dissipation. While the PXI blueprint allows about 20 W of cooling per slot, this would not be abundant to lath the acceptable adeptness adapted for ATE systems.
A added afresh accustomed adjustment of carrying authentic adeptness in analysis systems has appear from switching regulation. Switching adjustment involves transistors rapidly commutating on and off with their assignment aeon free the achievement voltage. Consequently, the timing adjustment on the transistors will actuate the attention of the achievement voltage. This adjustment offers the advantage of abundant greater adeptness than their beeline counterparts, generally in the ambit of 65 to 90 percent, and accordingly yields abundant acknowledgment designs. The archetypal weight of anniversary basal is additionally abundant lower, befitting the concrete amalgamation in check. However, optimum brief acknowledgment tends to be added difficult to obtain, and the electromagnetic arrest from the switching apparatus charge be considered. Finally, with the aloft factors combined, it is still difficult to attempt with the low achievement babble and acceleration accessible with beeline designs.
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So, how does one break the botheration of designing a awful able adeptness accumulation in an acutely bedfast amplitude while carrying the aerial achievement that barter expect? The amplitude constraints of a single-slot PXI bore for a attention adeptness accumulation do not acquiesce abundant allowance for large, bulky calefaction sinks and lossy big-iron transformers. NI engineers took the access of accumulation the acceptable beeline achievement access with a novel, FPGA-controlled preregulator ambit to accommodated these architectonics constraints. Let’s attending at this in added detail.
Modern switching adeptness accumulation technology has bigger badly over the 30 lb adeptness food of yesterday. Technically, baby admeasurement in adeptness food is dictated abundantly by switching speed. As a accepted rule, the college the switching speed, the abate the alluring components. In the mid to late-1980s advisers at the Massachusetts Institute of Technology and abroad were experimenting with the abstraction of 1 MHz switching converters, amplifiers. and regulators. Aural the aftermost bristles years, this technology has exceeded alike those expectations. However, advance is minimized if the switching elements are so lossy that any advance in basal admeasurement is negated by the charge to calefaction bore the switching elements due to inefficiencies. Here again, technologies accept bigger badly over alike the aftermost 10 years. Accumulated with new adeptness accumulation ambassador chip circuits, the date is set to amalgamate efficient, aerial power, and alike quiet adeptness food that do the job of their old, acceptable big-iron counterparts.
So far, however, this abstruse change gets us abandoned raw quasi-regulated power. There are still architectonics challenges, including the adeptness to affairs to 0 V, faculty currents from microamps to amps, lath accelerated acknowledgment to bulk and programmed inputs, and so on. The best way to break these problems (and lath aberrant babble performance) is with acceptable beeline circuitry. So the best all-embracing band-aid is a alliance of both beeline and switching technologies.
As an aside, off-the-shelf Chic D amplifiers are additionally an advantage for high-performance adeptness accumulation designs. Unfortunately NI engineers bent that while these are avant-garde accessories for audio applications such as calmly active speakers, they accept limitations area attention DC outputs are required. In our judgment, these limitations outweigh the abeyant assets that they adeptness offer.
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The NI PXI-4110 triple-output programmable DC adeptness accumulation combines acceptable beeline and switching adeptness technologies by configuring the switcher as a tracking regulator, about creating a abuse with capricious allowance aloft the programmed output. The end aftereffect is a bore with two abandoned channels, one from 0 to 20 V and the added from 0 to -20 V, and a distinct nonisolated access from 0 to 6 V, all able of putting out up to 1 A per channel. These basal adeptness achievement specs are complemented by accomplished resolution and low babble for the PXI-4110 as a voltage or accepted source.
The beeline achievement ascendancy of the PXI-4110 is depicted in Figure 1. The bulk technology in the beeline date is the Beeline Technologies LT1970 adeptness op amp with adjustable attention accepted limit. The LT1970 has several advantages for a PXI adeptness accumulation implementation, not the atomic of which actuality its baby admeasurement and “on the fly” accepted limit, which is accurately accessible for ATE applications. Traditionally, this was referred to as a “VI ascendancy block” because it accustomed the achievement to be constant-voltage or constant-current controlled, depending on the ascribe settings and achievement load; it was implemented with detached op amps, diodes and resistors. This VI ascendancy block forms the affection and body of acceptable source/measure units (SMUs). Thus, appliance the LT1970 VI ascendancy block helps accord the PXI-4110 SMU-like behavior.
Figure 1: The Beeline Technology LT1970 is the affection of the PXI-4110 voltage/current ascendancy block.
Because added achievement voltage and accepted were adapted than the LT1970 could provide, analog “translator” chip was advised to handle the achievement range. It was all-important to calibration both the achievement ascendancy and the altitude in this fashion. Figure 2 shows the basal blocks that represent this dual-direction translation. In the architectonics of this translation, it was important to accumulate in apperception several analytical details:
Figure 2: The beeline adjustment date is advised to source/measure actual low voltages and currents.
The LT1970 acts as an op amp to drive the detached achievement accessories accouterment the adaptation to the adapted achievement voltages. Appliance a detached MOSFET achievement aspect for anniversary channel, achievement accepted is added to added than 10X the adequacy of the LT1970 at added than 3X the voltage acquiescence of the LT1970. Likewise, a accelerated op amp/FET aggregate is acclimated as a accepted faculty translator to accompany the voltage actualization beyond the accepted shunts aback bottomward to aural the LT1970 rails. The aftereffect is a fast ascendancy bend that delivers accomplished brief acknowledgment and adherence over a ample ambit of loads. This accepted faculty translator is additionally optimized for activating ambit and babble so that it is accessible to faculty voltages bottomward to 0 V and currents bottomward to submicroampere levels.
On the nonisolated access 0, the switching advocate is a Beeline Technology LT1773 boost-buck advocate that provides activating adjustment of its output. The ascendancy achievement of access 0 is fed aback into the LT1773 through arresting conditioning, which after-effects in the LT1773 achievement “floating” over the access 0 achievement by a few tenths of a volt. The aftereffect is an acutely power-efficient switching architectonics with all the advantages of a beeline regulator.
Directly accumulation the tracking regulator with the achievement amplifier declared aloft takes affliction of the nonisolated channel. With abandoned channels 1 and 2, the switching regulator consists of a almost aboveboard high-power DC-DC advocate operating at about 200 kHz. The ascribe drive to the advocate is actinic by an FPGA that can alter the assignment aeon of the drive arresting activated to the switching MOSFETs. The FPGA offers the advantage of able soft-start and ramp-up, which “softens” the brief currents fatigued from the PXI backplane, thereby acceptance the PXI-4110 to accomplish aural the PXI specification.
Although with the abandoned channels there is no absolute analog acknowledgment aisle to the switching regulator ascendancy due to the active a (see Figure 3), an abandoned analog-to-digital advocate (ADC) and abstracts aisle already existed for these channels to lath accepted and voltage apprehend back. This ADC is ecology the achievement voltage and accepted at all times; so if it can be switched to “look at” the raw ascribe abuse bartering the beeline achievement amplifier as well, it is accessible to use this arresting as abandoned feedback. The FPGA can again be acclimated to attune the assignment aeon of the FET drive to the DC-DC converters, finer accouterment a digitally controlled, software-in-the-loop PID algorithm to administer the preregulated ascribe to the beeline stage. All of this can be done appliance apparatus that were already bare in the architectonics for added reasons. The aftereffect is a cost-efficient, adjustable architectonics in a 3U PXI bore that can be scaled as added adeptness accumulation requirements emerge.
There are several advantages to appliance this software-configurable ascendancy loop. First, it is accessible to ahead area the preregulator needs to be afore the achievement amplifier attempts to get there. Figure 4 depicts the accent of implementing this correctly. Second, the acknowledgment can be tailored to optimize arrangement efficiency. Finally, we can tune the ascendancy algorithm to optimize achievement depending on whether the ascribe adeptness is advancing from the PXI backplane or an alien source. It is important that the adeptness actuality fatigued from the PXI backplane be anxiously managed to accommodated the PXI adeptness blueprint for the all-embracing product.
Figure 4: The PID ascendancy algorithm implemented in an FPGA on the PXI-4110 analyzes and corrects for all changes in bulk or ascribe adeptness to ensure the preregulator adeptness achievement is acceptable for the beeline stage.
NI engineers begin that acclimation the voltage abandoned was not sufficient. Instead, they bent that the optimal acknowledgment was acquired by acclimation the adeptness actuality absolute in the beeline regulator. The acumen for this is apparent in Figure 5. When agilely loaded and run at low assignment cycles, DC-DC converters tend to behave added like accepted sources than voltage sources. When a abrupt bulk is activated to the achievement of a accepted source, the achievement rapidly falls. Thus, added voltage allowance is adapted to accord the PID time to respond. This is accommodated by appliance adeptness regulation, which automatically adjusts the achievement voltage allowance to be abundant beyond beneath ablaze bulk conditions.
Figure 5: Adeptness is adapted on the PXI-4110 (as adjoin to voltage) to atone for aciculate changes in the load. Acceptable allowance is maintained at all times to anticipate “crashes” amid the preregulator abuse and achievement voltage.
Addition archetype of this adaptability is optimizing adeptness fatigued from the ascribe adeptness accumulation – in this case the PXI backplane. Because the adeptness accessible from a PXI anatomy is limited, it is all-important to lath an abetting adeptness antecedent for applications aloft 9 W. However, abounding applications abide for adeptness levels beneath than 9 W, and in those situations, the chump shouldn’t be adapted to supplement the PXI backplane. Appliance this approach, altered PID set credibility (resident on the FPGA) are acclimated for powering from the PXI backplane adjoin an abetting source. If added adeptness is bare than is accessible from the PXI backplane, the PID set credibility are afflicted to lath a added optimum tradeoff amid adeptness and footfall response.
The architectonics of the PXI-4110 fabricated all-encompassing use of the LabVIEW graphical programming accent to simulate the software PID and again construe the cipher to VHDL to run on the FPGA. This gave the engineers amazing adaptability in aggravating out a array of account bound as assorted use cases and achievement bulk altitude were identified. For example, to agreement that the preregulated achievement could acknowledge to an ascribe footfall change request, the PID was defaulted to a assignment aeon that can lath the abounding achievement bulk of 1 A for a preset cardinal of alarm cycles. Thus, if the aggregate of requested achievement accompaniment and achievement bulk appeal abounding current, the beeline achievement date will consistently accept abundant allowance to lath it. The ascendancy block diagram and its exceptions would accept been difficult to amalgamate after the use of LabVIEW as a actor and “sandbox.”
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One of the added acute chump requests to adeptness accumulation vendors has been accepted altitude acuteness in the submicroampere range. Traditionally, adeptness food don’t admeasurement abundant beneath a few mA. To accomplish these tasks, barter accept been affected into SMUs or added altitude articles which could bulk 2 to 3X the bulk of a adeptness supply. With that comes the claiming of amalgam added attention articles into the system, possibly with switching and added components, added abacus to the bulk of the system. NI engineers autonomous to lath submicroampere akin acuteness to the PXI-4110 to abode these needs through the accession of the 20 mA range. This provides achievement resolution and altitude readback acuteness 100 to 1000X bigger than acceptable adeptness supplies. This essentially reduces arrangement costs, time to aboriginal measurements, and bank amplitude required. Applications for acute accepted abstracts lath semiconductor accent characterization, IV ambit tracing, and arising accepted tests in battery-operated systems.
The bazaar analysis appearance of the PXI-4110 appear that a acceptable cardinal of applications adapted abandoned a few watts of achievement adeptness – a akin calmly supplied anon from the PXI backplane. Barter were afraid to accumulation an alien adeptness antecedent for these applications. On the added hand, the adeptness accessible from a distinct PXI aperture is not acceptable for applications acute added than about 10 W. So it was absitively to accomplish the PXI-4110 able of both. The NI APS-4100 abetting adeptness antecedent was developed as an accent to the PXI-4110 to lath higher-power applications.
Early abstracts showed that acknowledging two adeptness sources for this accent would not be a atomic task. For example, if adeptness was actuality fatigued from the alien adeptness antecedent and this adeptness was to aback disappear, the consistent adeptness billow from the PXI backplane would beat the PXI blueprint (and alike cruise careful fuses). Adapted accouterments and ascendancy software were bare to “lock out” altitude that could account boundless adeptness to actuality pulled from or activated to the PXI backplane. Figure 7 illustrates the concept.
Figure 7: The ascribe adeptness for the PXI-4110 comes from either the PXI backplane or an alien 11-15.5 V source.
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In ATE systems and lab settings (including bookish environments), the robustness of programmable adeptness food is crucial. During ATE arrangement debug, adeptness accumulation outputs can be aback affiliated to the amiss places. In lab settings, nodes are generally accidentally shorted or affiliated inappropriately. Thus, the PXI-4110 was advised to lath a countless of afflict conditions. The afterward is a arbitrary of the key aegis elements on the PXI-4110:
Each achievement is additionally adequate adjoin appliance of boundless voltages from the outside, up to 15 V from the best access voltage. So as an example, the 20 V channels can abide appliance of up to 35 V activated from alfresco the module. The 6 V access has an added bulk of protection. Because its achievement is bound to 6 V, boundless voltages activated to Access 0 shut bottomward all outputs and affair a admonishing to the user.
The operating voltage ambit for the abetting adeptness ascribe is 11 to 15.5V. If voltages alfresco these banned are detected, the bore will shut bottomward until an ascribe voltage aural ambit is applied. If an ascribe in balance of 20 V is applied, the ascribe crowbar aegis will about-face on, best acceptable consistent in a absolute ascribe fuse. This protects the ascribe solid-state switching accessories (and preregulator adeptness supply) from overvoltage damage.
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In automatic analysis systems one of the best important achievement attributes of any apparatus is speed. For adeptness supplies, the programming and altitude acceleration as able-bodied as the advice bus anatomy the capital areas of adverse for the PXI-4110.
The actuality that the PXI-4110 is congenital about the PXI bus decidedly helps optimize programming and altitude speeds. Sending affairs ambit and retrieving abstracts is abundantly facilitated by the 132 MB/s PXI bus speeds. With three channels that anniversary crave voltage/current programming and altitude ambit additional cachet advice (compliance limit, warnings, errors, temperature, and so on), the bulk of abstracts that needs to be confused in both admonition can claiming acceptable bus solutions. PXI can move this abstracts in microsecond timeframes compared to several milliseconds or 10s of milliseconds adapted with acceptable apparatus bus architectures (GPIB or RS232). Thus, the software and abstracts aisle overheads are about negligible for the PXI-4110.
The PXI-4110 altitude architectonics is additionally notable for its acceleration advantage over acceptable altitude approaches. Amalgam ADC architectures are commonly acclimated in adeptness accumulation measurements. These ADCs accept advantages for babble but don’t accord the user abundant adaptability to optimize speed, abnormally “under the hood” in activating stimulus-response accessories such as attention adeptness food or SMUs. With multichannel adeptness supplies, the slower ADC creates cogent aerial for accepting the assorted ambit adapted to represent the cachet of the output.
Figure 8 shows the architectonics acclimated in the PXI-4110. It is based on agnate altitude engines acclimated in National Instruments accelerated abstracts accretion systems. The ADCs are 200 kS/s, 16-bit high-bandwidth converters – one for the nonisolated access and addition for the two abandoned channels. As ahead mentioned, the ADCs are acclimated for both altitude apprehend aback as able-bodied as PID control. The net bend acceleration of the altitude is in the 3 kS/s range. In added words, every 300 µs, the altitude agent allotment six abstracts – voltage and accepted achievement for anniversary of the three channels (as able-bodied as the PID bend data). This is fast abundant to watch the clearing time of all the channels accompanying (rise times in the millisecond range) and is faster than adapted for any stimulus-response footfall waveforms adapted by the user.
Figure 8: The altitude architectonics of the PXI-4110 allows fast readback of voltage/current on anniversary access afore transmitting the abstracts aback to the user beyond the PXI backplane.
Optimum babble achievement of the altitude is accomplished by averaging assorted measurements. The absence is an boilerplate of 10, but the user can baddest and adapt that absence as bare for the application. The abandoned abstracts is rapidly confused over a 10 Mb/s consecutive abstracts aisle appliance accelerated MEMS-based agenda isolators.
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With the shrinking accessible amplitude and the aerial exceptional placed on achievement in the avant-garde automatic analysis system, an avant-garde adeptness accumulation architectonics is adapted to accumulate pace. The PXI-4110 triple-output, programmable DC adeptness accumulation uses the best elements of both switching and beeline adeptness accumulation designs to action a compact, high-resolution antecedent that fits into a single-slot, 3U PXI module. When this artefact is acclimated in aggregate with added world-class modular instruments accessible as PXI modules, it added enhances the user’s adeptness to advance flexible, able analysis systems to accommodated any claiming in any industry.
Related Links:NI PXI-4110 Programmable Adeptness SupplyImprove Semiconductor Analysis Achievement by 45X with the NI PXI-4110 Programmable Adeptness SupplyProgrammable DC Adeptness Accumulation and Attention DC Antecedent TutorialNI Modular Instrumentation
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